COMMENT ⊗   VALID 00006 PAGES
C REC  PAGE   DESCRIPTION
C00001 00001
C00002 00002	DTE20 spec.  (look in KLDCP source code)
C00003 00003	DTE20 KL10 I/O Functions
C00005 00004	DTE20 PDP11 Registers
C00012 00005	DTE20 Operations
C00037 00006	EBUS PI CYCLE
C00046 ENDMK
C⊗;
DTE20 spec.  (look in KLDCP source code)
CONO PI,bit 22  clears only the requests initiated with CONO PI,bit 24.
In fact, that is the only way such a request can be cleared.

DTE20 is device 200 same as DC
PAG is device 10 same as IOP
AS is device 774 is unrestricted

When the console does an examine, does the MBOX look in the cache?

CONO PAG,E
  bit		function
  18		cache look (enables looking in the cache)
  19		cache load (enables writing into the cache)
  20		unused
  21		KL10 paging mode
  22		trap and paging enable
 23-35		executive base register (EBR)
DTE20 KL10 I/O Functions

CONO DTE0,E
  bit		func
 00-21		-
  22		set DPS5 10 REQ INT (1)
  23		clear DPS5 RELOAD PDP11 (1)
  24		set DPS5 RELOAD PDP11 (1)
  25		-
  26		clear DPS5 REQ 10 INT (1)
 27-28		-
  29		clear DPS5 10 TO11 NORM TERM (1) and DPS5 10 TO11 ERR TERM (1)
  30		clear DPS5 10 TO10 NORM TERM (1) and DPS5 10 TO10 ERR TERM (1)
  31		enable load PI0 ENABLE and PIA
* 32		bit → DPS3 PI0 ENABLE (1) if enabled by bit 31 
 33-35		bits → DPS3 PIA 4,2,1 (1)       "

* DPS3 PI0 ENABLE (1) is ignored since the 11 is privileged (EXT DIAG BUS CON)



CONI DTE0,E
  bit		func
 00-19		-
  20		-EXT DIAG BUS CON (always reads back as zero)
  21		INT1 PWR FAIL
  22		DPS5 10 REQ INT (1)
 23-25		-
  26		DPS5 REQ 10 INT (1)
  27		DPS5 10 TO11 ERR TERM (1)
  28		-
  29		DPS5 10 TO11 NORM TERM (1)
  30		DPS5 10 TO10 NORM TERM (1)
  31		DPS5 10 TO10 ERR TERM (1)
  32		DPS3 PI0 ENABLE (1)
 33-35		DPS3 PIA 4,2,1 (1)



DATAO DTE0,E
  bit		func
 00-22		-
  23		bit → DPS5 TO10 I BIT (1)
 24-35		bits → DPS2 EBHOLD 11-00 (1)
DTE20 PDP11 Registers

UNIBUS locations 174400 - 174427 are contained in a RAM in the DTE20.
These locations may not be written in byte mode.  Reading any RAM location
returns the last value written there.  Writing into certain RAM locations
has side effects indicated by the functions below.

DLYCNT	174400	(RAM)
DEXWD3	174402	(RAM)
  bit		func
 15-00		KL10 data bits 20-35



  bit		func
 15-00		KL10 data bits 4-19



  bit		func
 15-04		-
 03-00		KL10 data bits 0-3



TENAD1	174410	(RAM)
  bit		func
 15-13		address space
  12		bit → CNT5 DEP (1)
  11		* bit → CNT2 PROTECTION OFF (1)
 10-07		-
 06-00		KL10 address bits 13-19

* CNT2 PROTECTION OFF (1) is cleared by CNT4 DEX DONE although the corresponding
  bit in the RAM location remains set.



TENAD2	174412	(RAM)
  bit		func
 15-00		* KL10 address bits 20-35

* writing into the TENAD2 register sets CNT5 DEX START (1), which is cleared by
  CNT4 DEX DONE or INT1 MST CLR and can be read as STATUS bit 2 (inverted).



TO10BC	174414	(RAM)

DIAG1	174430
  bit	read				write (byte operations illegal)
 15-09	* EBUS DS00-06			** CNT3 DIAG DS 00-06 (1)
  08	CNT4 DEX (1)			-
  07	CNT4 TO10 TRANS (1)		*** CNT3 REMOVE STATUS
  06	CNT4 TO11 TRANS (1)		-
  05	CNT3 DIAG 10/11 (1)		CNT3 DIAG 10/11 (1)
  04	-				CNT5 SINGLE PLS (1)
  03	-				CNT3 DIAG KL10 (1)
  02	-				CNT3 DIAG SEND (1)
  01	-				-
  00	-				**** CNT3 DIAG COM START (1)

*    the "or" of TTL DS lines and:
      DS04 = CLK ERROR STOP, DS05 = CON RUN, DS06 = CON EBOX HALTED (EBOX HALT LOOP)
**   if EXT DIAG BUS CON (always true) CNT3 DIAG DS 00-06 (1) get ored with
     EBUS DS00-06 on the TTL bus.
***  if EXT DIAG BUS CON (always true) CNT3 REMOVE STATUS drives EBUS REMOVE
     DS STATUS which causes the ecl EBUS DS00-06 E lines to be driven from
     the ttl EBUS DS00-06 lines which are being driven from CNT3 DIAG DS 00-06.
**** CNT3 DIAG COM START (1) gets synchronized, then causes CNT3 STROBE (1)
     which goes out as EBUS DIAG STROBE for one clock period (8 10/11 ticks).  One
     period after CNT3 STROBE (1) clears, the entire DIAG1 register is cleared.

10/11 clock ticks are happening at 12.5 MHz = 80 ns. (1/2 MBOX rate)




DIAG2	174432
  bit	read				write (byte operations illegal)
  15	DPS4 ADR3 (CNT1 ADR 3)		-
  14	DPS4 ADR2 (CNT1 ADR 2)		CNT2 BUS DONE SET
  13	DPS4 ADR1 (CNT1 ADR 1)		-
  12	DPS4 ADR0 (CNT1 ADR 0)		-
 11-07	-				-
  06	-				reset (INT1 MST CLR)
  05	-				-
 04-01	-				loaded into CNT4 STATE COUNT
  00	-				-



STATUS	174434
  bit	read				write (byte operations permissible)
  15	DPS5 11 TO10 NORM TERM(1)	set DPS5 11 TO10 NORM TERM (1)
  14	-				clear DPS5 11 TO10 NORM TERM (1)
  13	DPS5 11 TO10 ERR TERM (1)	set DPS5 11 TO10 ERR TERM (1)
  12	DPS4 RAM = 0			clear DPS5 11 TO10 ERR TERM (1)
  11	DPS5 10 REQ INT (1)		set DPS5 10 REQ INT (1)
  10	-CNT4 DEX WD1			clear DPS5 10 REQ INT (1)
  09	DPS5 PAR ERR (1)		clear DPS5 PAR ERR (1)
  08	DPS5 REQ 10 INT (1)		set DPS5 REQ 10 INT (1)
  07	DPS5 11 TO11 NORM TERM (1)	set DPS5 11 TO11 NORM TERM (1)
  06	CNT6 E-BUF SEL			clear DPS5 11 TO11 NORM TERM (1)
					 and DPS5 NULL STOP (1)
  05	DPS5 NULL STOP (1)		set DPS5 11 INTERRUPT EN (1)
  04	DPS5 EBUS PARITY ERROR (1)	* clear DPS5 EBUS PARITY ERROR (1)
  03	-EXT DIAG BUS CON (always 0)	clear DPS5 11 INTERRUPT EN (1)
  02	CNT5 DEX START (0)		* set DPS5 EBUS PARITY ERROR (1)
  01	DPS5 11 TO11 ERR TERM (1)	set DPS5 11 TO11 ERR TERM (1)
  00	DPS5 11 INTERRUPT EN (1)	clear DPS5 11 TO11 ERR TERM (1)

* there is a bug whereby writing these bits with byte instructions won't work!



DIAG3	174436
  bit	read				write (byte operations illegal)
  15	-CNT1 SWAP SEL LT		-
  14	DPS4 PARITY (1)			-
 13-09	DPS7 CAP DATA 15 - 11		-
  08	DPS7 CAP DATA A00		-
 07-06	-				-
  05	-				CNT8 CAP DATA CLK
  04	CNT8 DATO PAR ERR (1)		clear CNT8 DATO PAR ERR (1)
					 and CNT8 DATO REC ERR (1)
  03	CNT5 WRITE EVEN PAR (1)		bit → CNT5 WRITE EVEN PAR (1)
  02	CNT8 DATO REC ERR (1)		-
  01	CNT8 NPR PAR ERR (1)		clear CNT8 NPR PAR ERR (1)
  00	-				bit → CNT5 TO10 BYTE MODE (1)
DTE20 Operations

Examine/Deposit

The PDP-11 can examine and deposit in KL10 lgoical memory (i.e., possibly
in the cache) by using the five RAM locations:
  DEXWD1, DEXWD2, DEXWD3, TENAD1 and TENAD2
For a deposit operation, the PDP-11 writes the 36 bit data word into
DEXWD1-3 and writes the deposit address into TENAD1-2.  For an examine,
it writes only the address and the data appears in DEXWD1-3.  None of these
registers are changed by the DTE20 and so their contents may be reused
for future examines and deposits.

The examine or deposit operation is initiated by writing into TENAD2.  Therefore
this should be the last location set up by the PDP-11 before the operation.
TENAD1 also contains several bits giving more information about the operation.
Bits 15-13 indicates the address space in which the operation is to be performed.
Bit 12 indicates whether the operation is to be an examine or a deposit.
Bit 11 is set to do an unprotected examine or deposit.  This bit acts in a very
stange way.  There is a flip flop for this bit in addition to the memory for
it in the RAM.  This flip flop is set from bit 11 on a UNIBUS DATO operation
to the TENAD1 register.  So, before the operation begins, the flip flop and
the RAM agree.  The protectedness of the examine or deposit is determined by
the flip flop rather than by the RAM location.  After the operation completes,
however, the flip flop is cleared (set to protected), although the RAM location
is unchanged.  Therefore, if another examine/deposit is attempted without first
writing into TENAD1 it will be a protected operation, independent of the state
of bit 11 in the TENAD1 RAM location.  DEC's reasoning behind this is to prevent
runaway deposits from clobbering more than one location.

THE DTE20 derives its clock from the EBUS 10/11 CLK line.  This is a 12.5 MHz
clock (1/2 MBOX rate) and is called 16 MHz on the CLK print.  This clock is used
to produce 8 clock time states in sequence: CNT7 SP CLK (1), CNT7 STATE CLK (1),
CNT7 STATE CLK+1 (1), CNT7 STATE CLK+2 (1), CNT7 WR CLK-1 (1), CNT7 WR CLK (1),
CNT7 WR CLK+1 (1) and CNT7 SHIFT CLK (1).  Each time state is on for one period
of the 10/11 clock, i.e. 80 ns.  In addition, there are four clocks which are
gated versions of some of the above 8, namely: CNT4 GD ST CLK, CNT4 GD WR CLK,
CNT4 GD WR CLK+1 and CNT4 GD SHF CLK.  These clocks are gated on by
-CNT4 INH CLK (1).  The DTE20 has three major state flip flops: CNT4 TO11 TRANS (1),
CNT4 TO10 TRANS (1) and CNT4 DEX (1).  These flip flops are set in sequence by
CNT4 GD ST CLK as long as CNT4 STATE HOLD (1) is false.  CNT4 STATE HOLD (1) is
clocked every CNT7 SP CLK (1).  It may be set while in one of the major states
by some condition for that state.

Writing into TENAD2 sets CNT5 DEX START (1) which causes CNT4 STATE HOLD (1) to
be set on the next SP clock when the DEX (1) major state is true.  This keeps
the DTE20 in the DEX major state until CNT4 STATE HOLD (1) is cleared which will
happen when CNT5 DEX START (1) is cleared which will happen on CNT4 DEX DONE or
INT1 MST CLR.  CNT4 DEX (1) being true enables the DEX minor state decoder.
It decodes the low three bits of the CNT4 STATE COUNT counter.  This counter
is cleared every time a new major state is entered.  So as soon as the DEX
major state is entered, the decode for zero, CNT4 DEX ADR1 is true.  The counter
counts on every CNT4 GD ST CLK (except where noted below).  Since major state
changes occur on the same clock, the counter will attempt to clear and count
every time there is a major state change (clear wins).  Thus when we stop in
some major state, the counter will be in zero for one clock period (8 10/11 clocks)
and then count to one for one period, etc.  So each decode is true for exactly
one period and comes true on the CNT4 GD ST CLK.

CNT4 DEX ADR1 forces CNT1 ADR 3,2,1,0 to be 0100 (4) which is the RAM word
address (UNIBUS byte address 10) of the TENAD1 word.  Since CNT1 RAM CYCLE GO
is low, the selector on the RAM address inputs select CNT1 ADR 3,2,1,0 and the
RAM reads out the TENAD1 word.  In the DEX major state, every CNT4 GD SHF CLK
will cause a CNT2 E-BUF CLK unless the operation is an examine and we are in
the minor state CNT4 DEX WD1.  The E-BUF selector is set by CNT6 E-BUF SEL to
load the low 16 bits of DPS2 E-BUF from the RAM outputs.  The state of the high
order bits is irrelevant.  So in the CNT4 DEX ADR1 minor state the low 16 bits
of the E-BUF register are loaded from the RAM TENAD1 word.  The next DEX minor
state is CNT4 DEX ADR2.  In this state, the RAM address is forced to 0101 or
word address 12, the address of TENAD2.  Again, the E-BUF register is set to
load the low 16 bits from the RAM and shift the original low 16 bits left by 16
places.  So when the E-BUF register is clocked, it will wind up with the
complete KL10 23 bit address in the low part of the E-BUF register and address
space in bits 4-6.  At the same time (CNT4 GD SHF CLK) as the E-BUF is loaded
with TENAD2, CNT4 TRANS REQ (1) is set and on the very next clock pulse
(CNT7 SP CLK (1)) CNT4 INH CLK (1) is set, inhibiting further GD type clock
pulses.  CNT4 TRANS REQ (1) is driven on the EBUS PI00 line if either
DPS3 PI0 ENABLE (1) or EXTN DIAG BUS CON (always true) is asserted.

The EBOX will service the EBUS PI00 request by setting EBUS CS04-06 to 000
and EBUS F00-02 to 100 = PI SERVED and asserting EBUS DEMAND.  This will
generate CNT7 PI SERVED, CNT7 PI LEVEL 0 and CNT7 SEL PI LEV.
CNT7 PI SERVED and CNT7 SEL PI LEV cause CNT6 SEND CONTROL which, together
with CNT7 PI LEVEL 0 sets CNT6 TRAN ACT (1).  CNT6 SEND CONTROL is also
wired to one of EBUS D08,09,10,11 depending upon which DTE20 it is.  This
causes the controller number to be sent back to the EBOX as a bit number.

The EBOX will drop EBUS DEMAND and determine the highest priority controller.
Its number will be encoded on EBUS CS00-03 and EBUS F00-02 will be changed
to 101 = PI ADDRESS IN.  After a delay the EBOX will again assert EBUS DEMAND.
The DTE compares EBUS CS00-03 with its hardwired physical number and if a
match occurs it sets CNT7 PHY NO. SEL.  CNT7 PI ADR IN will be set as a result
of seeing EBUS DEMAND and EBUS F00-02 = 5.  CNT7 SEL PI LEVEL, CNT7 PI ADR IN
and CNT7 PHY NO. SEL together cause CNT6 E-BUS SEND OP.  This signal, together
with CNT4 DEX (1) and CNT6 TRAN ACT (1) cause -CNT6 OP CODE 1 and with CNT5 DEP (1)
cause CNT6 OP CODE 2.  -CNT6 OP CODE 1 causes CNT6 BUS SEL A which causes
CNT6 BUS SEL Y which causes CNT6 EMIX EN.  CNT6 E-BUS SEND OP causes CNT6 BUS SEL Z
which together with -CNT6 OP CODE 1 enables DPS3 E-BUS MIX 00,01,02,06.  These
bits are selected from DPS3 E-BUF 04,05,06 and CNT2 PROTECTION OFF (0) resp.  and
drive EBUS D00,01,02,06.  Therefore the address space from TENAD1 bits 15-13
which are in E-BUF bits 04-06 are driven on EBUS D00-02.  The Q bit (EBUS D06)
is driven from CNT2 PROTECTION OFF (0).  CNT6 BUS SEL Z enables EBUS D03,04,05,07
to be driven from CNT6 TRAN ACT (1), CNT6 OP CODE 1, CNT6 OP CODE 2 and GND resp.
So the function is driven on EBUS D03-05.  The function is 100 for examine and
101 for deposit.  CNT6 BUS SEL A enables EBUS D12-19 to be driven from
DPS2 E-BUF 12-19.  CNT6 BUS SEL Y enables EBUS D23,24,25,28 to be driven from
DPS2 E-BUF 23,24,25,28 resp, and CNT6 EMIX EN enables EBUS D20-22,26,27,29-35
to be driven from their respective DPS2 E-BUF bits.

In summary:
   EBUS bits	    from			use
     0-2	E-BUF 04-06			address space from TENAD1 15-13
     3-5	TRAN ACT,OP 1,OP 2		function
      6		PROTECTION OFF (0)		Q bit
     7-11	not driven
    12-35	E-BUF 12-35			13-35 are the KL10 address from
						  TENAD1 06-00 and TENAD2 15-00

CNT6 E-BUS SEND OP asserts CNT6 TRANS (EBUS XFER) and CNT6 ACK (EBUS ACK).

The EBOX will read the EBUS data lines and drop EBUS DEMAND.  When this happens
CNT6 IOP SENT (1) will be set which will cause CNT4 TRANS REQ (1) to clear
which will drop the request on EBUS PI00.  EBUS DEMAND clearing will drop
CNT7 PI ADR IN which will clear CNT6 E-BUS SEND OP which will drop CNT6 TRANS
(EBUS XFER) and will also drop CNT6 OP CODE 2 if the function was a deposit.
CNT6 OP CODE 2 clearing will set a flip flop on the INT1 page which, on the
next CNT7 STATE CLK+2 will clear INT1 BUS COMP (0).  This will clear the D
input to the CNT4 INH CLK (1) flip flop which will clear on the next
CNT7 SP CLK.  CNT4 INH CLK (1) clearing will clear the INT1 page flip flop
and will set INT1 BUS COMP (0).  The CNT4 STATE counter will begin counting
again and the next minor state will be CNT4 DEX WD1.  This will happen on
CNT4 GD ST CLK.  It is on CNT7 SP CLK (1) that CNT4 INH CLK (1) tries to
set and by this time CNT4 DEX ADR2 will have cleared, so CNT4 INH CLK (1)
won't set.  (See later on for the continuation of the DEX minor states).
If the operation was an examine then CNT6 OP CODE 2 will not have been set
in the first place, so the gated clocks remain off.

The EBOX microcode notices the interrupt request flip flop and goes off to
some code which will perform the function specified on the EBUS.  In the
case of an examine, the function was 4, namely DATAO.  The microcode will
perform a COND/EBUS CTL with magic numbers field = 026.  This causes
APR EBOX DISABLE CS and APR EBUS F01 E.  APR EBOX DISABLE CS forces the
EBUS CS00-06 lines to zero.  The EBUS F00-02 lines will be 010, the EBUS
DATAO function.  The microcode will then assert EBUS DEMAND.  This looks
like an ordinry DATAO except that the CS lines say zero instead of the
device address.  Devices that give a PI function of DATAO or DATAI assume
that the next DATAO or DATAI will be for them independent of the CS lines.
This is possible since the PI logic will not begin a new PI cycle since
the microcode has set CON PI CYCLE and this inhibits setting PI5 LOAD and TEST.
If the operation was a deposit, then the PI function was 5, a DATAI and the
microcode will perform a COND/EBUS CTL with magic numbers field 027.  This
operates the same way as DATAO except that EBUS F02 is asserted generating
function 011.  Again, the microcode will assert EBUS DEMAND.

If the operation is an examine, then CNT6 IOP SENT (1) will cause CNT6 SP DATAO
to be true which will cause CNT6 E-BUF SEL to be false.  This selects the
EBUS as the input to the E-BUF register.  EBUS DEMAND is anded with
CNT6 SP DATAO to produce CNT6 TRANS (EBUS XFER) and CNT2 E-BUF CLK which
loads DPS2 E-BUF with EBUS data.  EBUS DEMAND anded with CNT6 IOP SENT (1)
produces CNT6 ACK (EBUS ACK).  The EBOX will clear EBUS DEMAND which will
clear CNT6 IOP SENT (1).  This will cause another flip flop to set on the
INT1 page which will eventually cause the gated clocks to start up again
and the CNT4 state counter to resume counting (see second paragraph above
this one for description of how this happens).

If the operation is a deposit, then the CNT4 STATE counter and CNT4 DEX minor
state decoder will have started again, independent of the EBUS starting up
a DATAI cycle.  One or the other of these two will occur first and they
are brought together via the CNT6 DEP STROBE (1) flip flop.  The CNT4 DEX
minor states will be described first.  In the case of a deposit, the CNT4 DEX 
minor states will also be restarted; however, DPS2 E-BUF will have already
been loaded from the DATAO cycle performed by the EBOX in response to the
PI00 request.

The next CNT4 DEX minor state is CNT4 DEX WD1.  It sets CNT1 ADR 1,0 giving
RAM address 3 (word address 6).

For examine, the RAM data inputs are selected by CNT2 DPS4 SEL 2,1 which
are set to 10 by CNT4 DEX WD1.  This selects DPS4 SPM 03-00 for input to
the RAM bits 03-00.  CNT1 EBH CYC is false, so the DPS4 SPM 03-00 lines are
selected from DPS2 E-BUF 00-03.  CNT4 DEX WD1 will also enable CNT4 GD WR CLK
to generate CNT1 WR PLS which will clock the RAM loading E-BUF 00-03
into DPS4 DATA 03-00.  This stores the high four bits of the examine data
into the low four bits of DEXWD1.  CNT4 DEX WD1 for examine also inhibits
CNT2 E-BUF CLK on CNT4 GD SHF CLK so the E-BUF register is not changed
during the CNT4 DEX WD1 minor state.

For deposit, CNT6 E-BUF SEL is false, enabling DPS2 E-BUF to select the RAM
for the low 16 bits.  The RAM address is set to DEXWD1 as above and
CNT2 E-BUF CLK occurs on CNT4 GD SHF CLK loading DEXWD1 into the low 16 bits
of the E-BUF.

The next CNT4 DEX minor state is CNT4 DEX WD2.  It sets CNT1 ADR 1 giving
RAM address 2 (word address 4).

For examine, the RAM data inputs are selected by CNT2 DPS4 SEL 2,1 which
are set to 11 by CNT4 DEX WD2.  This selects DPS2 E-BUF 04-19 for input to
the RAM bits 15-00.  CNT4 DEX WD2 will also enable CNT4 GD WR CLK
to generate CNT1 WR PLS which will clock the RAM loading E-BUF 04-19
into DPS4 DATA 15-00.  This stores bits 4-19 of the examine data into
DEXWD2.  CNT2 E-BUF CLK happens on CNT4 GD SHF CLK and CNT6 E-BUF SEL is false
so the E-BUF register shifts bits 20-35 into bits 04-19.

For deposit, CNT6 E-BUF SEL is false, enabling DPS2 E-BUF to select the RAM for
the low 16 bits and shift E-BUF bits 20-35 into E-BUF bits 04-19.  The RAM
address is set to DEXWD2 as above and CNT2 E-BUF CLK occurs on CNT4 GD SHF CLK
loading DEXWD2 into the low 16 bits of the E-BUF.

The next CNT4 DEX minor state is CNT4 DEX WD3.  It sets CNT1 ADR 0 giving
RAM address 1 (word address 2).

For examine, the RAM data inputs are selected by CNT2 DPS4 SEL 2,1 which
are set to 11 by CNT4 DEX WD3.  This selects DPS2 E-BUF 04-19 for input to
the RAM bits 15-00.  CNT4 DEX WD3 will also enable CNT4 GD WR CLK
to generate CNT1 WR PLS which will clock the RAM loading E-BUF 04-19
into DPS4 DATA 15-00.  This stores bits 20-35 of the examine data into
DEXWD3.  CNT2 E-BUF CLK happens on CNT4 GD SHF CLK and CNT6 E-BUF SEL is false
so the E-BUF register shifts.

For deposit, CNT6 E-BUF SEL is false, enabling DPS2 E-BUF to select the RAM for
the low 16 bits and shift E-BUF bits 20-35 into E-BUF bits 04-19.  The RAM
address is set to DEXWD3 as above and CNT2 E-BUF CLK occurs on CNT4 GD SHF CLK
loading DEXWD3 into the low 16 bits of the E-BUF.  The E-BUF now contains the
data to be returned for deposit when the EBOX does a DATAI.

For a deposit the DTE must wait until the EBOX does a DATAI, or if it is
already doing a DATAI, it must send the data that is in the E-BUF register.
CNT4 DEX WD3 enables CNT6 DEP STROBE (1) to be set on the trailing edge
of CNT4 GD SHF CLK which is right after the E-BUF had the low 16 bits of
deposit data shifted in.  It also asserts CNT6 DEPST which enables
CNT4 INH CLK (1) to be set on the next CNT7 SP CLK (1).  This will keep
us in the CNT4 DEX WD3 minor state until CNT4 INH CLK (1) is cleared.
When the EBOX does the DATAI function, CNT3 DEMAND and CMT6 IOP SENT (1)
cause CNT6 ACK (EBUS ACK).  CNT7 DATAI and CNT4 DEX (1) and CNT6 IOP SENT (1)
cause CNT6 BUS SEL X,Y,Z,A and CNT6 EMIX EN.  These signals cause the E-BUF
to drive the EBUS data lines.  When the E-BUF has been loaded with the deposit
data and been given a chance to settle, CNT6 DEP STROBE (1) will be set
(as described above) which is anded with EBUS DEMAND to produce CNT6 TRANS
(EBUS XFER). When the EBOX drops EBUS DEMAND, CNT6 IOP SENT (1) will be cleared
and CNT4 INH CLK (1) will be reset the same way as it was for examine (described
above).

In the case of examine, the clock is not stopped in the CNT4 DEX WD3 minor
state.

In either case the clock resumes and the DTE goes into the CNT4 DEX DONE
minor state.  This clears CNT5 DEX START (1).  On the next CNT7 SP CLK (1)
CNT4 STATE HOLD (1) will clear and on the next CNT4 GD ST CLK the DTE will
go to the next major state and clear the CNT4 STATE counter.
EBUS PI CYCLE

(Refer to PIC1-PIC5 prints)

The EBOX detects EBUS PI01 - PI07 E on enabled channels if the PI
system is active and always detects EBUS PI00 E (strobed into PI1 PIRn
at PI5 LOAD time).  The channel number of the highest priority request
is encoded on PI2 PI4,2,1 and PI2 REQ is asserted.  At PI5 TEST time
the PI system tries to grab control of the EBUS.  If not successful,
PI5 TEST stays true (no PI5 LOAD occurs) until it is successful.
When it succeeds in getting the EBUS, PI5 BUS PI GRANT will be set.
This enables the TTL EBUS data bits to drive the ECL EBUS data bits;
sets the PI5 CYC START flip flop; drives EBUS CS04 - 06 E from PI2 PI4,2,1
(i.e., broadcasts the selected PI channel); enables EBUS CS00 - 03 E to be
driven from PI2 SEL PHY 8,4,2,1 (not used until later); sets EBUS F00 E to
1 causing function 4 = PI SERVED to be sent on the EBUS function lines;
disables further requests by asserting PI5 INHIBIT REQ which inhibits
further PI5 LOAD and PI5 TEST assertions PI CYC START being set causes
PI2 STATE HOLD to drop.  On the next (MBOX) clock tick, PI2 TIM1
will be set and the PI timer will be set to 010101.  PI2 TIM1 clears
PI5 CYC START which causes PI2 STATE HOLD to again be asserted.  This
in turn holds the PI2 TIMn bits in their present state.  The PI timer
will count up with each clock tick until the high order bit (100000)
goes on causing PI2 TIMER DONE.  This causes PI2 STATE HOLD to drop
so that on the next clock, the PI2 TIMn state register will advance
to PI2 TIM2.  Also, the timer will load with 001001.  This again clears
PI2 TIMER DONE which asserts PI2 STATE HOLD which holds PI2 TIM2.
PI2 TIM2 asserts EBUS DEMAND E (we therefore waited 12 ticks = 480 ns
between asserting EBUS CS04 - 06 E and EBUS F00 - 02 E and when we
asserted EBUS DEMAND E).  Those controllers interrupting on the
broadcast PI channel put a 1 on the EBUS Dnn line whose bit number
corresponds to their hardwired backpanel controller address (controller
2 asserts EBUS D02 E).  No acknowledge or transfer is asserted.  The
PI2 timer will count until 100000 when we will go to PI2 TIM3 and new
timer value 011100 (we will have waited 24 ticks = 960 ns).  PI2 TIM3
stobes EBUS D00 - 15 E into PI2 PHY NO. 00 - 15 which are priority
encoded into PI2 SEL PHY 8,4,2,1 and driven on EBUS CS00 - 03 E.
EBUS DEMAND E drops when PI2 TIM2 does.  When the timer counts out
(5 ticks = 200 ns) we go to PI2 TIM4 and new timer value 010101.
PI2 TIM4 causes EBUS F02 E to latch up, sending function 5 = PI ADDRESS IN.
The timer counts out after 12 ticks = 480 ns and we go to PI2 TIM5 and
new timer value 010001.  PI2 TIM5 asserts EBUS DEMAND E but prevents
the timer from counting until PI2 TRAN REC is asserted.  The selected
(by EBUS CS 00 - 03 E) controller, when it sees EBUS DEMAND E places
the function word it wants executed on the EBUS D lines and asserts
transfer (XFER).  XFER is synchronized in the EBOX and becomes
PI2 TRAN REC.  This re-enables the timer which count 16 ticks = 640 ns
(to deskew the EBUS D lines) and we go to PI2 TIM6 and new timer
value 010011.  PI2 TIM6 keeps EBUS DEMAND E up and forces PI2 TIMER DONE
which inhibits the timer from counting and causes it to repeatedly
load with 011100.  PI2 TIM6 also causes PI2 STATE HOLD to remain
asserted as long as -CON PI CYCLE B is true (note that ordinarily
PI2 STATE HOLD is asserted by -PI2 TIMER DONE which is now held false).
PI2 TIM6 causes PI2 READY which causes CON INT RQ (if not CON INT DISABLE
which can be set by the microcode) which is the condition the EBOX microcode
looks at to decide to interrupt.  PI2 TIM6 also causes the EBUS D07 - 10 E
lines to be driven from PI2 SEL PHY 8,4,2,1.  When the microcode sets
CON PI CYCLE, PI2 STATE HOLD drops causing PI2 TIM6 to drop and PI2 TIM7
to set; this drops EBUS DEMAND E.  At the same time the timer is loaded
with 011100.  After 5 ticks = 200 ns we go to PI2 COMP and load the timer
with 110001 forcing PI2 TIMER DONE which holds PI2 STATE HOLD off.
PI2 COMP drops the EBUS F02 E latch and enables PI5 EBUS PI GRANT to clear
on the next clock pulse, at which time PI2 COMP also clears.


Summary of EBUS PI Cycle

1)  Device asserts EBUS PIn.

2)  EBOX selects highest priority PI channel and broadcasts it on EBUS CS04-06, and
    sets EBUS F00-02 to 4 = PI SERVED.

3)  EBOX delays 480 ns and asserts EBUS DEMAND.

4)  Device that is interrupting on the broadcast PI channel asserts EBUS Dnn where
    nn is the hardwired controller number of the device.  Channels are 0-7, DTEs
    are 8-11 and the DIA is 15.

5)  EBOX delays 960 ns and stobes the EBUS and determines the controller with the
    lowest number that wants to interrupt.  Its controller number is broadcast
    on EBUS CS00-03 and EBUS DEMAND is dropped.

6)  EBOX delays 200 ns and sets EBUS F00-02 to 5 = PI ADDRESS IN.

7)  EBOX delays 480 ns and asserts EBUS DEMAND.

8)  The controller whose address is being broadcast in EBUS CS00-03 places
    a function word on the EBUS data lines when it sees EBUS DEMAND and it
    also asserts EBUS XFER.

9)  EBOX delays 640 ns and then sets the interrupt request flip flop to the
    microcode.  EBUS DEMAND remains asserted as well as the function, CS and
    DATA lines.